Exception Handling Sequence for IRQ

When an exception happens:

• CPU switches mode to IRQ mode (MODE = 0x12)
• CPSR is saved into the SPSR_irq register
• R15 (PC) is saved into R14_irq (i.e. the Link Register or return addr for the IRQ mode)
• Ibit of the CPSR is set to 1 disabling further IRQs
• R15(PC) is forced to address 0x00000018
• CPU executes LDR PC,[PC,#0x18] at 0x00000018
• Which loads the PC with the address of OS_CPU_ARM_ExceptIrqHndlr()

The CPU executes the code in OS_CPU_ARM_ExceptIrqHndlr(), then OS_CPU_ARM_ExceptHndlr() (found in OS_CPU_A.S).

OS_CPU_ARM_ExceptHndlr() calls OS_CPU_ExceptHndlr() (found in BSP.C) to determine the source of the interrupt and handle it accordingly.

When OS_CPU_ARM_ExceptHndlr() returns from OS_CPU_ExceptHndlr() it calls OSIntExit() (in case of task interrupted) which determines whether higher priority tasks has been made ready to run by the exception handler or, whether we simply need to return to the interrupted task.

If the interrupted task is still the highest priority task, OSIntExit() returns to OS_CPU_ARM_ExceptHndlr() which simply returns to this task.

If there is a more important task OSIntExit() calls OSIntCtxSw() (see OS_CPU_A.S) which takes care of switching to the more important task.